Metal-oxide-semiconductor (MOS) transistors, such as MOS field effect transistors (MOSFET), are used in the manufacture of integrated circuits. MOS transistors include several components, such as a gate electrode, gate dielectric layer, spacers, and diffusion regions such as source and drain regions. An interlayer dielectric (ILD) is typically formed over the MOS transistor and covers the diffusion regions.
Electrical connections are made to the MOS transistor by way of contact plugs that are typically formed of a metal such as tungsten. The contact plugs are fabricated by first patterning the ILD layer to form vias down to the diffusion regions. The patterning process is generally a photolithography process. Next, metal is deposited in the vias to form the contact plugs. A separate contact plug is formed down to the gate electrode using the same or a similar process.
One problem that can occur during the fabrication of a contact plug is the formation of a contact-to-gate short. A contact-to-gate short is a short circuit that occurs when the contact plug is misaligned and comes into electrical contact with the gate electrode. One conventional approach to preventing contact-to-gate shorts is by controlling registration and critical dimensions (CDs). Unfortunately, for transistors with gate pitches (gate length+space) at or below 100 nanometers (nm), CD control for gate and contact dimensions needs to be less than 10 nm and the registration control between gate and contact layers also needs to be less than 10 nm to deliver a manufacturable process window. Thus, the likelihood of a contact shorting to a gate is very high. This problem becomes more prevalent as transistor gate pitch dimensions are scaled down further because the critical dimensions become much smaller.